1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device having a circuit controlling an operation of a memory array based on a result of address decoding.
2. Description of the Background Art
A conventional semiconductor memory device will be described with reference to FIG. 19. A conventional semiconductor memory device as shown in FIG. 19 includes a decoder 901 decoding an address, internal circuits 902#0-902#n, and power supply control circuits 904#0-904 #n.
Decoder 901 decodes an address in response to a bank activation signal ACT and outputs decoding signals B1(0)-B1(n) and B2(0)-B2(m) (in the drawing, m=1) (hereinafter decoding signals B1(0)-B1(n) will be collectively referred to as decoding signal B1, and decoding signals B2(0)-B2(m) will be collectively referred to as decoding signal B2). Power supply control circuits 904#0-904#n are provided corresponding to internal circuits 902#0-902#n, respectively. Power supply control circuit 904#0-904#n are each activated in response to decoding signal B1. Based on the decoding signal B1, one of power supply signals V(0)-V(n) supplied from power supply control circuits 904#0-904#n as outputs is activated (hereinafter, power supply signals V(0)-V(n) are collectively referred to as power supply signal V).
Internal circuits 902#0-902#n are each activated when decoding signals B1 and B2 and power supply signal V corresponding thereto are all activated. The power supply control circuit is a circuit for supplying power to a part of the internal circuit and is employed for reducing the current consumption of the internal circuit in a standby state and for reducing the number of elements in the internal circuit.
The structure of the conventional semiconductor memory device described above has the following problem. With reference to a timing chart shown in FIG. 20, the problem of the conventional semiconductor memory device will be described. In FIG. 20, character B indicates a decoding signal (corresponding to an output of decoder 901 shown in FIG. 19), character ACT indicates a bank activation signal for activating a memory cell array, character V indicates a power supply signal (corresponding to one of power supply signals V(0)-V(n) shown in FIG. 19), and character STATE indicates a state of an internal circuit (corresponding to one of internal circuits 902#0, . . . , 902#n shown in FIG. 19) operating based on decoding signal B.
In FIG. 20, transition from a standby cycle to an active cycle occurs at time t1. Bank activation signal ACT is set to an H (a logical high) level (VCC) in the active cycle and to an L (a logical low) level (GND) in the standby cycle. During the standby cycle, all decoding signals B are at an L level and the internal circuit is not in an operation (STATE is at an L level).
With reference to FIG. 20, bank activation signal ACT is turned to an H level at the outset of the active cycle. Decoding signal B rises to an H level at time t2 (&gt;t1) in response thereto. Power supply signal V is activated at time t3 (&gt;t2) in response thereto. The internal circuit is activated at time t4 (&gt;t3) in response thereto (that is, STATE is turned to an H level).
As described above, power supply signal V is activated in response to decoding signal B1. Hence, power supply signal V is not activated until time t3 after the activation of decoding signal B1 at time t2. Therefore, the state of the internal circuit STATE is not determined before time t4 after time t3.
Thus, in the structure of the conventional semiconductor memory device, at least time (t4-t2) is required to turn the internal circuit into a desired state (that is, to turn STATE into an H level), whereby high speed operation cannot be achieved.